1. Field of the Invention
The present invention relates to a having a bit line reset circuit (precharge circuit).
2. Description of the Related Art
FIG. 9 is a schematic diagram showing a structure of a prior art synchronous DRAM (SDRAM). In the description hereinafter, generally a signal S or a signal line S is complementary with a signal *S or a signal line *S, respectively.
The SDRAM includes a DRAM core 1A of bank 0 and a DRAM core 1B of bank 1. The DRAM core includes a memory cell array, a row decoder, a column decoder, column gates and sense amplifiers.
A clock CK and a clock-enable signal CKE are applied through a clock buffer circuit 2 to each part in the memory and synchronous operation is performed.
A command decoder 3 issues a command corresponding to a combination of input signals, which are a chip select signal *CS, a row address strobe signal *RAS, a column address strobe signal *CAS and a write enable signal *WE, at the time when the clock rises. In the case where all of these signals are low, for example, a mode register set command is issued, and an operation mode is set by an address provided through an address buffer circuit 4 to a mode register 5. The operation mode has a CAS latency, a burst length and a burst type. An active command ACT, a read command READ and a write command WRIT, etc. from the command decoder 3 are provided to a control circuit 6A or 6b, which in turn provide various control signals to the DRAM cores 1A and 1B in response to the respective commands.
The bank select bit A23 which is the MSB of the bits A23 to A12 held in a higher order address buffer register of an address buffer circuit 4 causes one of the DRAM cores 1A and 1B to be selected, while the row address bits A22 to A12 cause a word line in the selected DRAM core 1A or 1B to be selected. The lower order address of A11 to A0 is loaded in a column address counter 7A or a column address counter 7B thereby to select a column in the selected DRAM core 1A or 1b. In reading data, the data on the bit line pair of this column is read out on a data bus line pair and retrieved outside through a data buffer circuit 8. In writing data, the data held in an I/O data buffer circuit 8 is transmitted through the data bus line pair and the column gates to a bit line pair and written in the memory cell selected by the word line. In the case where the burst length is 2 or more, a column address counter 7A or 7B is incremented by clock, so that data are read or written successively.
FIG. 9 schematically shows a circuit connected to a pair of bit lines BL and *BL as part of the DRAM core 1a.
The bit line BL is divided into a cell-side bit line BLC and a bit line BLS on sense amplifier side by a transfer gate 10. The bit line *BL is divided into a cell-side bit line *BLC and a bit line *BLS on sense amplifier side by a transfer gate 11. To each of the bit lines BLC and *BLC a plurality of memory cells are connected. In FIG. 9, for simplicity, only memory cells 12 and 13 are shown connected to the bit lines BLC and *BLC, respectively. To the bit line BLC a dummy cell 14 for a plurality of memory cells is connected, and to the bit line *BLC a dummy cell 15 for a plurality of memory cells is connected.
Between the bit line BLS and the bit line *BLS, A bit line reset circuit 16 for resetting a potential of the bit lines BL and *BL, a sense amplifier 17 for amplifying the potential difference between the bit line BL and the bit line *BL and a column gate 18 for turning on/off the data line pair between the bit lines BLS and *BLS are connected.
Now, referring to FIG. 10, an explanation will be given of the operation of reading data from the memory cell 12 in the case where the reset potential of the bit lines BL and *BL is Vss (0 V) and `H` (an internal power supply potential Vii, for example, 2.5 V) is held in the memory cell 12.
(1) Active Command ACT
The following operation is performed in response to an active command ACT issued from the command decoder 3.
The higher order address of A23 to A12 is held in the higher order address register of the address buffer circuit 4, the DRAM core 1A is selected by a bank select bit A23=`0`, and a word line, a dummy word line and a gate control signal BT corresponding to the row address of A22 to A12 is activated, so that the transfer gates of the memory cell 12 and the dummy cell 15 and the transfer gates 10 and 11 are turned on. Positive charges 2Q and Q are provided from the memory cell 12 and the dummy cell 15 to the bit lines BL and *BL, respectively, so that the potential of the bit lines BL and *BL are increased from Vss by 2.DELTA.V and .DELTA.V, respectively. Then, the sense amplifier 17 is activated, and the potential difference .DELTA.V, for example, 0.2 V between the bit lines BL and *BL is amplified so that the potentials of the bit lines BL and *BL become Vii and Vss, respectively.
(2) Read Command READ
Then, a read command READ is issued from the command decoder 3 and the following operation is performed.
The column address of A11 to A0 is loaded in a column address counter 7A. A column gate 18 corresponding to the column address is turned on, and the data on the bit lines BL and *BL is transmitted through the data bus lines to the I/O data buffer 8, and is thus outputted outside. In the process, a pipeline processing is performed in synchronization with the clock. In the case where the burst length is 3, for example, the column address counter 7A is incremented twice for each clock under the same row address, and the data can be sequentially read out of the other two bit line pairs.
(3) Precharge Command PREC
Then, the following operation is performed in accordance with the issue of a precharge command PREC from the command decoder 3.
As shown in FIG. 10, the word lines and the dummy word lines are inactivated to terminate the restore operation. Then, the sense amplifier 17 is inactivated while activating the bit line reset circuit 16 for a period tr, thereby resetting the bit line to a potential Vss. The gate control signal BT is inactivated to close the transfer gates 10 and 11.
In the case where the DRAM core 1B is accessed after the command READA or WRITA is issued to the DRAM core 1a, the DRAM core 1B can be operated in parallel with the last reset operation of the DRAM core 1a. The reset operation in the DRAM core 1A thus is hidden.
In accessing the DRAM core 1A again with activating another word line, the next operation cannot be started before expiry of the reset period. The cycle of the clock CLK is about 10 ns. However, the reset time Tr is comparatively long and about 30 ns due to a multiplicity of memory cells connected to long bit line with comparatively large parasitic capacitance and resistance. Such problem is also encountered for a non-burst mode, and hence in a normal DRAM having a single bank.
For solving this problem, JP First Publication No. 8-221983 discloses such a method that another bit line reset circuit is also connected between BLC and *BLC, and the transfer gates 10 and 11 are turned off at a time point when the potential difference between BLC and *BLC is considered to have reached near the full amplitude during the operation of (2) above, while continuing the operation of (2) by the sense amplifier in parallel with the operation (3) of the memory cell described above.
Specifically, after the second rise of *CAS in the burst mode with column address changing under the same row address, the word line rise up, next the gate control signal BT becomes low to turn off the transfer gates 10 and 11. Then, BLC and *BLC are precharged to potential Vii/2 by the bit line reset circuit. The gate control signal BT falls down at timing after the lapse of a predetermined time from the activation of the sense amplifier 17.
When the reset potential is Vss=0 V, the change in the voltage Vc of the memory cell capacitor during the amplification operation of the sense amplifier 17 is expressed approximately as Vc=Vii{1-EXP(-t/.tau.)}, where a time constant .tau.=(the resistance of both the transfer gates at the memory cell and the bit line BL1).times.(the capacitance of both the memory cell capacitor and the bit line BL1). As seen from this formula, the voltage Vc changes slowly up to Vii. For the above-described small voltage .DELTA.V to be secured, the transfer gates 10 and 11 cannot be turned off until the voltage Vc reaches about 95% of the maximum voltage Vii. The above publication discloses the case in which the burst length is 4. For the burst length of 2, however, the operation (3) above will be started at about the end of the operation (2), therefore the two operations cannot be performed in parallel.
Further in the above publication which describes a circuit for precharging the bit lines on the memory cell side to a potential Vii/2, the load is larger because of precharging bit line pair, resulting in longer precharging time.